Astera Labs
Purpose-built connectivity solutions for intelligent systems
Connectivity solutions • Signal Conditioning • PCIe • Heterogeneous Compute • Hyper-scale Data Center
51 - 200
Senior Design Verification Engineer
April 10
🏢 In-office - Bay Area
Astera Labs
Purpose-built connectivity solutions for intelligent systems
Connectivity solutions • Signal Conditioning • PCIe • Heterogeneous Compute • Hyper-scale Data Center
51 - 200
Description
• Contribute to the functional verification of complex ASIC designs • Responsible for full lifecycle of verification from planning to debugging • Collaborate with software and system validation teams • Execute test plans in emulation platforms • Utilize coding and problem-solving skills • Be part of a team focused on flexibility, interoperability, and reliability • Located in Silicon Valley headquarters with global R&D centers
Requirements
• Bachelor’s in Electrical Engineering (Master's preferred) required • ≥5 years’ experience verifying SoC for Server, Storage, and Networking applications • Proficiency in System Verilog, C, C++, Python, or other scripting languages • Familiarity with industry-standard simulators and revision control systems • Ability to work independently and prioritize tasks • Entrepreneurial mindset with a customer-focused approach • Authorized to work in the US
Benefits
• Base salary range USD 130,000.00 – USD 185,000.00 • Opportunity to work with a global leader in connectivity solutions • Work in a dynamic and innovative environment • Health insurance and other benefits • Generous vacation and paid time off policy • Opportunity for professional growth and development
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