Astera Labs
Purpose-built connectivity solutions for intelligent systems
Connectivity solutions • Signal Conditioning • PCIe • Heterogeneous Compute • Hyper-scale Data Center
51 - 200
Tech Lead Firmware Engineer (DDR technologies)
May 23
🏢 In-office - Bay Area
Astera Labs
Purpose-built connectivity solutions for intelligent systems
Connectivity solutions • Signal Conditioning • PCIe • Heterogeneous Compute • Hyper-scale Data Center
51 - 200
Description
• As an Astera Labs Senior/Staff Firmware Engineer, you will be designing and developing Firmware for enabling DDR technologies for future looking products defined by Astera Labs CXL memory solutions.
Requirements
• Bachelor’s in Electrical engineering / Electronics / Computer Science or related fields. • 5+ years of experience in developing Firmware using C in Embedded environments. • Good knowledge in DDR Technology internals (DDR Training, DDR RAS, PMIC, RCD etc.) • Ability to debug DDR related issues.
Benefits
• We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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