RTL Digital Design Engineer, Principal
March 16
🏢 In-office - Bay Area
Description
• Responsible for the micro-architecture and design of High-speed IO interfaces • Design and deliver fully verified, high-performance RTL • Participate in silicon bring-up and validation for blocks owned
Requirements
• BSEE with 8+ years of work experience or Master’s degree in related field with 5 years of work experience • Proficiency in Verilog/System Verilog for RTL development • Experience in Processor and Digital Signal Processing blocks • Exposure to Mixed-signal designs, Computer Architecture & Arithmetic • Strong understanding of ASIC design flow and CAD tools • Strong interpersonal skills and ability to work well in a team environment
Benefits
• Hybrid work schedule • Competitive compensation ranging from $180K to $300K • Opportunity to work on cutting-edge technology in Large Language Models and AI • Inclusive and empowering work environment
Apply Now