Staff Engineer, Design Verification
August 28
🏢 In-office - Bay Area
Description
• Key contributor to the ORAN SoC product design verification team • Collaborate with FW & design team for product requirement definition and microarchitecture study • Participate in the verification of novel ORAN SoC functional blocks for high-performance applications such as LTE and sub-6 GHz 5G cellular base stations • Interface with functional leads in project coordination for schedule tracking on deliverables and dependencies • Provide technical advice to young engineers to ensure the quality of work • Opportunity for engineers with 5+ years of industrial experience to grow their technical career and leadership
Requirements
• Master's and/or bachelor’s degree in engineering (or equivalent) in EC/ EE/ CS • Eight or more years of experience in design verification with proven experience in full chip verification from test plan development to tape-out sign-off • Good understanding of the complete verification life cycle (test plan, testbench through coverage closure) • Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc.) from the scratch • Proficient in System Verilog, Verilog/VHDL, UVM and C; and scripting languages like Python, Perl and Tcl/Shell • Experience in developing IP/ Subsystem/ chip-level System Verilog and UVM based test bench environments, writing System Verilog Assertions (SVAs), with embedded software design and testing • Strong knowledge about multiple testbench architectures, industry-standard interfaces/ protocols (AXI, AHB, APB etc.) • Experience in Cadence Design Tools/ Environments and exposure to Cadence VIPs/ UVCs is plus • Track record of successfully executing block or chip-level verification plans • Excellent communication and presentation skills, energetic and self-motivated • Work effectively with an off-site/ offshore design and verification teams across locations
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