Physical Design Engineer Lead
July 27
🏢 In-office - Bay Area
Description
• Responsible for designing, developing, and executing physical design implementation of low-power and high-performance SoC • Work with the RTL and System design teams to drive the physical design of the device in early design cycle • Design, implement and verify suitable methodology that meets the QoR goals • Resolve design and flow issues related to the physical design, identify potential solutions, and drive execution. • Deliver physical design of entire SoC, complete with specification, flow and automation • Interface with the RTL design team to drive design modifications to resolve physical design issues and implement ECOs • Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality • Interact with tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new vendor tools and functions
Requirements
• Bachelor’s degree (Master’s preferred) in Electrical Engineering or comparable engineering discipline • 8+ years of proven experience in physical design • Experience with logic synthesis • Experience in physical design and timing closure for advanced nodes • Experience in Cadence EDA tools for physical design and verification • Experience in floor planning, power planning, CTS specification, place & route, and timing closure • Experience in CPF/UPF specs design and implementation • Be able to work with cross-functional teams, IP, and EDA vendors
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