Principal Engineer, RF PLL Design
March 11
🏢 In-office - Bay Area
Description
• Technical leadership in developing custom RF, analog, and mixed signal IPs • Hands on contribution on all aspects of the design of high-performance RF frequency synthesizers in advanced CMOS processes • Supervising layout activities and performing post-layout LPE simulations and analysis • Working closely with cross functional engineering teams • Presenting to peers and management • Partnering with System and Digital Engineers in method and algorithm design • Assisting Test Engineers in test plan design and production ATE solutions • Post-silicon bring-up, performance characterization, optimization, and debug using lab instruments
Requirements
• MSEE minimum, PhD preferred • 12+ years of hands-on experience in high-performance RF, Analog, and Mixed Signal IC design • Technical knowledge of RF CMOS fundamentals and transistor level design • Experience in transistor-level design of RF Frequency Synthesizer related circuits • IC layout and verification proficiency • Strong problem-solving and analytical skills • Proficiency in development tools such as Cadence Virtuoso, Matlab, etc. • Strong sense of urgency and ability to work on multiple tasks simultaneously • Excellent written and verbal communication and presentation skills • Desirable: experience in IoT, WiFi, Bluetooth, wide tuning range RF VCO and RF PLL designs
Benefits
• Office locations in CA • Hybrid remote/office work environment • Balanced workplace • Continuous improvement, learning, and collaboration • Position can be based in San Diego or San Jose
Apply Now
