Rivos, a high performance RISC-V System Startup targeting integrated system solutions for Enterprise.
April 17
đ Hybrid â Bay Area
Rivos, a high performance RISC-V System Startup targeting integrated system solutions for Enterprise.
⢠Define Architecture and Microarchitecture for Data Parallel accelerator based memory subsystem components including Cache, Interconnects, HBM, DDR, LPDDR ⢠Develop Performance Models in C++ for design space exploration to achieve optimal performance under area and power constraints ⢠Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance ⢠Develop Performance Verification tests to ensure quality of model and design ⢠ML Workload analysis with a focus on improving Memory subsystem performance
⢠In-depth knowledge of Memory subsystem architecture, microarchitecture and design including caches, NOC and LPDDR/DDR/HBM ⢠Expert Performance Modeling using C/C++ ⢠Knowledge and experience with common performance benchmarks and workloads in the ML space ⢠Ability to work well in a team and be productive under aggressive schedules ⢠Proficiency in System Verilog, C or C++, scripting languages such as Python ⢠Experience with high-level simulators for power estimation is a plus ⢠Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated
⢠Fun, creative and flexible work environment ⢠Shared vision to build products to change the world
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