Sr. Digital Implementation Engineer

April 5

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Alif Semiconductor

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Changing the way developers create connected, secure, low-power, high-performance edge processing solutions

IoT • Semiconductors • AI/ML • Wireless

201 - 500

💰 $113.4M Venture Round on 2022-03

Description

• You will be responsible for creating turn-key solutions to support cutting-edge Cellular IoT device. This is a unique opportunity to define a groundbreaking new system with few legacy constraints. • As a Sr. Digital Implementation Engineer, you will own the netlist delivery (to Physical Design) of various blocks and chip top level by ensuring the integrity and quality of the RTL database and robust hand-off methodology. This position requires expert knowledge of ASIC synthesis flow (including STA/DFT and IP integration).

Requirements

• Significant experience with ASIC Synthesis Flow, Constraint Generation/Validation and Timing Closure • Familiarity with DFT (Tessent) and back-end (Cadence) tools Hands-on experience with digital logic synthesis for power and area optimization • Experience in low power design issues, tools, and methodology including UPF power intent specification • Proficient in Verilog/SV/Tcl/Perl/Python • Highly motivated to debug and resolve CAD tool flow issues • Self-starter with good analytical, problem solving and communication skills • Bachelor’s degree in Electrical Engineering, a related discipline, or equivalent experience. • Strong expertise with Design Compiler or Genus. • Experience with IP integration • Experience with Synthesis, LEC, DFT, BIST • Experience with Cadence Timing and ECO Flow • Experience with Clock Domain Crossing (CDC) Analysis • Experience with timing corner selection and library models • Proven track record of successful deep submicron technology node tapeout (including Silicon bring-up) • Detailed hands-on knowledge of all aspects of timing closure (including OCV, noise, crosstalk, IR-drop, power/voltage domains/UPF, DFT)

Benefits

• Define and document synthesis methodology and scripts/flows • UPF flow for defining power intent (at block and chip level) • RTL and Netlist hand-off checks (LEC) • Interface with Physical Design for floor-planning and timing closure • Assist with design partitioning and floorplan. • Analyze STA results and facilitate RTL changes and Timing ECOs with front-end and back-end teams