RTL Digital Design Engineer, Senior Staff
March 17
🏢 In-office - Bay Area
Description
• Be responsible for the micro-architecture and design of the High-speed IO interfaces. • Own design, document, execute and deliver fully verified, high performance, area and power efficient RTL to achieve the design targets and specifications. • Design of micro-architecture and RTL, synthesis, logic and timing verification using leading edge CAD tools and semiconductor process technologies. • Design and Implement logic functions that enable efficient test and debug. • Participate in silicon bring-up and validation for blocks owned.
Requirements
• BSEE 8+ years of meaningful work experience / Master’s degree preferred in electrical engineering, Computer Engineering or Computer Science with 5 years of meaningful work experience. • Experience in micro-architecture and RTL development (Verilog/System Verilog), focused on Processor, Digital Signal Processing blocks. • Exposure to Mixed-signal designs, Computer Architecture & Arithmetic is required. • Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis. • Strong interpersonal skills and an excellent teammate.
Benefits
• Hybrid work model • Competitive compensation range: $161.3K - $260K
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