IC ASIC RTL Design Engineer
August 28
🏢 In-office - Bay Area
Description
• Ownership of all aspects of the design process, from analysis of the design approach and tradeoffs, to specification, through RTL implementation • Delivery of a robust, high performance design that meets the timing, area, reliability, testability, and power requirements set by the cross-functional engineering team • Work with system software, architecture, and microarchitecture experts on the functional and performance requirements in the development of novel, high throughput engines for processing, moving, storing, and scheduling of data • Support functional verification, from the involvement in setting the verification strategy, to the development of the test plan, through the execution of the testing and coverage phases • Support for performance validation, to ensure that the product meets the strenuous performance demands of modern data centers across diverse use cases • Support silicon bringup and post-silicon testing of mission critical functions
Requirements
• Proven industry experience and successful track record in designing and building high-performance interface logic and/or processing pipelines • Experience with PCIe Gen5/6 and CXL at the Transaction Layer is preferred • High-performance pipelines with multi-threaded datapaths and ordering capabilities • Demonstrating expert capability in designing blocks such as DMA controllers and queueing/doorbell engines • Expert knowledge of SystemVerilog • Good knowledge of Python, Perl, or other scripting languages • Junior role: Minimum BSEE/CE + 3 years or MSEE/CE + 2 years experience • Mid role: Minimum BSEE/CE + 7 years or MSEE/CE + 5 years experience
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