Principal Engineer, Digital Design SoC
August 28
🏢 In-office - Bay Area
Description
• Collaborate with design engineers to develop novel SoC products for connectivity and communications • Contribute to product definition and detailed device performance and functional requirements specifications • Support teams to bring the SoC device to successful mass production
Requirements
• MS/Ph.D. in EE or equivalent and 20 or more years of experience in SoC development and mass production • Knowledge of ARM/RISC Architectures, Multi-core CPU operation and system memory partition/hierarchy • Experience with AMBA AXI/AHB/APB Protocol bus architecture specification and implementation • Thorough knowledge of Verilog/VHDL/System Verilog languages and front-end tools such as simulation, linting, clock-domain crossing checking, formal verification • Proven knowledge of constraint definition, synthesis, static timing analysis and complete Front to Back SoC design/implementation flow • Understanding of SCAN ATPG, BIST, DFT/DFM and fault coverage analysis • Proven knowledge of System Verilog/UVM methodology and other advanced design verification techniques • Proficiency of programming/scripting languages such as C/C++, Perl, Tcl, and Python • Great collaborator and team player with effective communication/presentation skills and aggressive schedule/quality result driven mentality
Benefits
• Comprehensive group health plan • Matching 401(k) • Training reimbursement • Various paid leaves (vacation, sick, holidays, maternity/paternity leave, jury)
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