Staff Engineer, ASIC Digital Design
August 28
🏢 In-office - Los Angeles
Description
• Design and integrate SERDES controller, PCS, PMA functional blocks • Micro code development for network processor • Network processor architecture, throughput analysis and optimization • Front-to-back ASIC digital design and verification – RTL through physical implementation • Define & review synthesis constraints for functional blocks • Functional issues debugging and timing closure issues debugging • Work with System, Software, RF, Analog, and Test teams and provide the necessary support
Requirements
• MS/Ph.D. EE/CS preferred • 10 or more years of experience in digital SoC development required • Industrial design experiences PCIE/JESD/Ethernet controller & PCS and respective SERDES PHY digital (PMA) • Strong knowledge on CPU bus protocols and designs such as AXI/AHB/APB and DMA • Solid design skill in Verilog / SystemVerilog RTL for complex SOC functional blocks in network products • Solid experience in static timing analysis, defining timing constraints and exceptions • Proficient in (Verilog/VHDL) and SystemVerilog RTL coding, LINT, CDC checking • Experience in using Synopsys CoreConsultant IP generation tools is a plus • Experience bringing highly integrated mixed-signal SoCs to commercial mass production • Experience with embedded systems, wireless protocols, power management, signal processing, and standard digital interfaces • Proven knowledge of SystemVerilog assertions, checkers, and other design verification techniques • Knowledge of languages such as C/C++, Perl, Tcl, and Python • Strong communication and presentation skills • Team player with a strong sense of urgency to complete projects on time
Benefits
• Comprehensive group health plan • Matching 401(k) • Training reimbursement • Various paid leaves (vacation, sick, holidays, maternity/paternity leave, jury)
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