Sr. DDR IP Design Engineer (Silicon Engineering)

July 23

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SpaceX

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SpaceX designs, manufactures and launches the world’s most advanced rockets and spacecraft

Falcon 9 and Falcon Heavy Rockets • Dragon Cargo and Crew Spacecraft • Merlin Rocket Engines • Draco and SuperDraco Thrusters • PICA-X high performance heat shield material

1001 - 5000

Description

• Own the high quality release of the Memory Controller IP for SpaceX SoC designs • Responsible for Memory Controller/PHY IP core development and integration • Collaborate with chip architects and software engineers to develop high performance Memory controller/PHY solutions • Support silicon bring-up, performance, and power characterization for memory subsystems

Requirements

• BS in Electrical Engineering, Computer Engineering, or Computer Science • 8+ years of experience working with ASICs and the VLSI design flow • Experience in RTL development and verification using Verilog and/or SystemVerilog • MS or PhD in Electrical Engineering, Computer Engineering, or Computer Science (preferred) • Knowledge of DDR/LPDDR DRAM protocols • Experience in Memory Controller and PHY IP development • Experience working with Memory IP, Error Checking Code (ECC) • Familiarity with DFT and writing DFT friendly RTL • Experience with AMBA AXI, ACE-Lite, and CHI interfaces • Programming skills in C, PERL/Python • Great communication and interpersonal skills

Benefits

• Comprehensive medical, vision, and dental coverage • 401(k) retirement plan • Short & long-term disability insurance • Life insurance • Paid parental leave • 3 weeks of paid vacation • 10 or more paid holidays per year • 5 days of sick leave per year • Access to long-term incentives like company stock and bonuses