Staff/Sr. Staff PHY Design Engineer
March 11
🏢 In-office - Bay Area
Description
• Responsible for Low-power WiFi, BT/BLE micro-architecture and design • Involved in high-level product specifications, RTL development, Algorithm collaboration • Develop Digital Signal Processing engines for wireless communication systems • Develop micro-architecture and SystemVerilog RTL • Analyze and optimize design • Develop design, verification and analysis tools • Collaborate with Verification, Validation, and Physical Design teams • Provide guidance on Floor planning, constraints, and timing closure
Requirements
• BSEE or MSEE with exp. in ASIC dev. or FPGA prototyping • 7+ years RTL design using Verilog, SystemVerilog • Understanding of Digital Signal Processing theory • Experience in WiFi/BT Physical Layer • Ability to work independently and proactively identify issues • Experience with RTL design tools like Incisive/VCS • Experience in synthesis, placement, timing closure • Enjoy debugging and problem solving in a team env. • Exp. in Low Power design with multiple domains • Exp. with Python, Perl, Tcl, C/C++, shell scripts • Exp. with lab debug, multi-team, multi-site env. • Exp. with ASIC and FPGA synthesis flows • Exp. using PowerArtist/Joules for feedback
Benefits
• Join a team of brilliant people with various backgrounds • Emphasis on working smart and celebrating successes • Opportunity to work with big technology in a small company • Opportunity to learn and experience different aspects of work • Playground for people seeking awesomeness
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